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Today, semiconductors lie at the heart of ongoing advances across the electronics industry. The introduction of new technologies, especially nanometre technologies with 14 nm or smaller geometry, has allowed the semiconductor industry to keep pace with increased performance-capacity demands from consumers. This has brightened the prospects for future industry growth.

However, new technologies come with new challenges. Smaller die sizes increase the probability of some errors. Errors in ICs are highly undesirable. Here’s a list of some possible issues that arise while manufacturing chips.

The possibility of faults may arise even after fabrication during the packaging process.

With all these issues in mind, it becomes vital to test every chip before it can be shipped and in fact, test it after every level of manufacturing.

Testing does not come for free. Modern microprocessors contain more than 1000 pins. They pack a myriad of functionalities inside them. If any single transistor inside a chip becomes faulty, then the whole chip needs to be discarded. We, consumers, do not expect faulty chips from manufacturers. But identifying that one single defective transistor out of billions is a headache. We may need to test every functionality with every possible combination. If testing is done that way, then the time-to-market would be so high that the chips may never reach the consumers. So, how do we tackle this? We use a methodology to add a feature to these chips. The methodology is called DFT; short for Design for Testability. And the feature it adds to a chip is ‘testability.’

So, does testing guarantee that the chip will never be faulty again?

No, faults can arise even after the chip is in consumer’s hands. A chip may misbehave anytime if it is exposed to a very high temperature or humid environment or due to aging.

Want a live explanation? If you have an unlocked processor, you can try to overclock your CPU using this tutorial. But would you do it? Please don’t!

Overclocking is a method to increase the system frequency and voltage above the rated value.  An improperly configured overclocking can mess up with timing metrics and cause instability. Prolonged overclocking would overheat and stress out your system to shorten the lifespan of your computer. This may cause intermittent faults in the chip and random crashes in the future. Adding to this, it may void your warranty too. This example is just one high-level explanation of how a fault may occur in real life.

Verification proves the correctness and logical functionality of the design pre-fabrication. The process is done after the RTL (Register Transfer Logic) design is coded with hardware description languages like VHDL or Verilog. It is done using a testbench in a high-level language. This is performed only once before the actual manufacturing of chip. In industry, this is done using formal verification processes like UVM (Universal Verification Methodology) using System Verilog. Verification is a vast topic on its own and we will cover it in this VLSI track and link it here soon.

In contrast, testing tries to guarantee the correctness of the manufactured chips at every abstraction level of the chip design process. Testing needs to be performed on each manufactured chip because each one of them has an equal probability of being faulty during the fabrication or packaging process. By doing testing, we are improving the quality of the devices that are being sold in the market.

Let’s segue into the career aspect of these two stages for a moment.

Here are a few terminologies which we will often use in this free Design for Testability course. Don’t fret if you can’t completely understand them yet, we will be covering them in-depth in this course.

Testing: An experiment in which the system is put to work and its resulting response is analyzed to ascertain whether it behaved correctly.

Diagnosis: Process for locating the cause of misbehavior in the circuit if it happened.

Defect: Refers to a flaw in the actual hardware or electronic system.

Fault: It is a model or representation of defect for analyzing in a computer program.

Error: It is caused by a defect and happens when a fault in hardware causes line/ gate output to have a wrong value.

Failure: This occurs when a defect causes misbehavior in the circuit or functionality of a system and cannot be reversed or recovered.

Fault Coverage: Percentage of the total number of logical faults that can be tested using a given test set T.

Defect Level: Refers to the fraction of shipped parts that are defective. Or, the proportion of the faulty chip in which fault isn’t detected and has been classified as good.

where Y is the yield, means the fraction of the chips fabricated that are good.

Testing is carried out at various levels:

There is an empirical rule of thumb that it is ten times more expensive to test a device as we move to the next higher level (chip → board → system). As we move to higher levels, more components are integrated, which makes the fault detection and localization much more difficult and expensive.

Here are a few possible sources of faults:

Faults can be classified into various subcategories.

DFT techniques are broadly classified into two types:

These are a collection of techniques or set of rules (do’s and don’ts) in the chip design process learned from design experience to make design testability more comfortable to accomplish. Basically, these are the rules that have been gathered over time after experiencing various errors.

In this technique, extra logic and signals are added to the circuit to allow the test according to some predefined procedure.

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