From Wikipedia, the free encyclopedia. An LVS tool enables accurate circuit verification because it is able to measure actual device geometries across a full-chip for a complete accounting of physical. LVS stands for Layout vs Schematic. Layout vs Schematic Verification (LVS). What is LVS? In ASIC physical implementation, once layout is generated, it must follow all the design rules for successful manufacturing and must match the. A LVS rule deck is a set of code, which is written in Standard Verification Rule Format (SVRF) or TCL Verification Format (TVF), which guides the.